This invention relates generally to charge coupled devices (CCDs), and more particularly relates to the design of charge coupled devices for high-speed imaging.
High-speed imaging is important for a wide range of applications, such as high-speed photography and video. Typically, a high-speed imaging application requires the acquisition of a sequence of image frames at an accelerated rate, resulting in a high rate of image frame data collection. For example, frame rates of greater than 1 million frames per second can be required for specialized imaging applications.
Many solid state imagers, such as CCDs, require a fixed duration of time for transferring a frame of acquired image data from on-chip image acquisition locations, such as an array of pixels, to off-chip locations for display or processing. With this constraint, it can occur with a conventional imager that the time required to transfer an acquired image frame from on-chip pixel sites to an off-chip location is comparable to or greater than the image acquisition time set by the frame rate of a high-speed imaging application. In such a scenario, image data from an acquired image frame cannot be transferred from pixel sites with a speed sufficient to enable acquisition of image data in the next succeeding image frame duration. The image transfer time thereby in general sets the maximum speed at which an imager can acquire images, and correspondingly limits the frame rate that can be accommodated by an imager.
There have been suggested various CCD imager designs that enable accommodation of an image transfer duration that is comparable with an image acquisition period. Many such designs employ the use of an image data storage region located on-chip, e.g., as a frame storage array separate from an imaging pixel array, or as a storage channel provided at or adjacent to a pixel site itself. Typically such storage regions are provided with an overlaying opaque blocking layer that prevents exposure of the storage region by a scene being imaged, such that the stored image data is preserved for transfer off-chip at a later time and/or at a slower speed than that provided by the image acquisition duration.
Such on-chip storage configurations are known to impose various limitations on imager performance. For example, for conventional imager designs, on-chip area that is employed for charge storage regions is typically taken from pixel areas that would have been employed for acquiring images; as a result, the pixel fill factor of the imager is greatly reduced over that of an imager without on-chip storage, and the sensitivity of the imager is correspondingly reduced. In addition, so-called image smear can occur in pixel data transferred from a pixel array to a frame-storage array.
These drawbacks are exacerbated for high-speed imaging applications in which a number of images are to be acquired in rapid succession. If on-chip area is to be provided for temporarily storing image data from a sequence of acquired images, the extent of the image data storage area must be commensurate with the number of images in the image sequence to be acquired. This typically results in significant imager sensitivity reduction and/or increased image smear. Thus, in general, for high-speed imaging applications, it has come to be expected that degradations in image quality must be accommodated, and in particular that high imaging sensitivity cannot be achieved at high image frame rates.